Single-trial detection of auditory cues from the rat brain using memristors

Implantable devices hold the potential to address conditions currently lacking effective treatments, such as drug-resistant neural impairments and prosthetic control. Medical devices need to be biologically compatible while providing enhanced performance metrics of low-power consumption, high accuracy, small size, and minimal latency to enable ongoing intervention in brain function. Here, we demonstrate a memristor-based processing system for single-trial detection of behaviorally meaningful brain signals within a timeframe that supports real-time closed-loop intervention. We record neural activity from the reward center of the brain, the ventral tegmental area, in rats trained to associate a musical tone with a reward, and we use the memristors built-in thresholding properties to detect nontrivial biomarkers in local field potentials. This approach yields consistent and accurate detection of biomarkers >98% while maintaining power consumption as low as 4.14 nanowatt per channel. The efficacy of our system’s capabilities to process real-time in vivo neural data paves the way for low-power chronic neural activity monitoring and biomedical implants.

Fig. S3: System and timing details. (A) Schematic of the envisioned system in operation.The neural signal is acquired by the electrode (1), amplified (2) and a low-pass filtered (3).The memristor is alternatively connected to either the live feed, or connected to the transimpedance amplifier (TIA) (4).Telemetry (5) processes the memristor resistive readings.The ArC TWO board acting as finite state machine powers the amplifier and active filter, and orchestrates the alternation (CTRL) of the two configurations in (4).(B) Channel topology schematic of the ArC TWO instrument used in the experiment.If ADC+ is not grounded, the ADC reading measures the current into the channel, if grounded, the ADC reading measures the voltage at the channel.Adapted from (37), (2020) Springer-Nature CC-BY.(C) Timing diagram showing the voltage applied to the top electrode of the memristor.During the bias phase, the neural signal is applied to the memristor for  , marked as solid line overlapping the live input.During the read-out phase, a .  sub-threshold voltage is applied to read the device without altering its current state.A   period includes delay time between phases.Telemetry uses readings every 70 samples for processing; additional readouts (in red) enhance monitoring and will not occur in real applications.(D) Circuit system diagram depicting the memristor switching between two configurations.In bias phase it connects to an external LFP, with voltage monitored at the top terminal.In read-out phase it is connects to a .  reading voltage, with a TIA read the current through the device.Here, the optimum threshold value was identified as 0.01.Here, the optimum threshold value was identified as 0.022.(A) Channel WB27 was input to a memristive device, (B) and the resistive response of the device was monitored.We can observe the signal was similar to the initial channel WB27, and the resistance successfully performs encoding of the LFP event class within the light blue windows.(C) ROC curves using "maxdiff", "maxdrop" and "batch".(D) Optimization process to select an optimum threshold, in this case equal to  = ..(E) Detection metrics for the "batch" method.

Fig. S14. Channel variability analysis, example 2. (A)
Channel WB21 was input to a memristive device, (B) and the resistive response of the device was monitored.Channel WB21 exhibited peaks that were more difficult to detect, and this led to a noisier shape of the memristive device response.(C) ROC curves using "maxdiff", "maxdrop" and "batch".(D) Optimization process to select an optimum threshold, in this case equal to A=0.004.(E) Detection metrics for the "batch" method show decreased performance due to the less distinct LFP signal input to the memristive device.S1.Hardware Resource Utilization and Power Estimation for FPGA Implementation.Detailed summary of the hardware resource utilization, dynamic power and energy estimation for the FPGA-based implementation of our system.Utilizing the Xilinx Artix-7 xc7a100tcsg324-1 and Vivado 2022.2 tool, we retrieved the consumption of Look Up Tables (LUTs) and Flip Flops (FFs).Dynamic power was estimated through post-implementation timing simulations, which involved generating a Switching Activity Interchange Format (SAIF) file.This file reflects the activity of internal nodes to ensure an accurate dynamic power estimation.Finally, we estimated the energy per operation considering a batch of N=70 samples, with resistance values quantized as 5-bit integer data.S2.Area and Power Estimation for ASIC Synthesis: Detailed summary of area, dynamic power, and energy estimation for the ASIC-based synthesis of our system.Cadence Genus tool was used on an ASIC 180 nm process at 1.8 V, and the values were scaled respectively targeting Multi-Gate HP 20nm at 0.9V and Bulk 65nm at 1.1V, using (57) Here, channel refers to the number of neural recording channels used in the system.For (33) the power and energy were evaluated at a sampling frequency of 10kHz, to enable comparison with state-of-the-art CMOS ASIC.

Movie S1. Real-time detection of memory tasks
Online auditory cue detection based on memristive integrating sensor system.The lower blue trace represents local field potentials recorded with implanted microwire in the ventral tegmental area of an awake freely moving rat.The upper trace is the memristive response to the local field potential applied to it.Green lines denote the presence of an auditory cue, also played in the background of the video.Cyan lines indicate the corresponding detections that follow.The LFP regions of interest are also highlighted.

Fig. S4 .
Fig. S4.Segment of the Local Field Potential recording obtained from 9 microwires implanted in the rat's brain.Dashed red lines mark instants when the auditory cue was presented to the animal.Following these cues, a discernible pattern emerges in the collective neural activity.The specific channel utilized in this experiment is identified as channel WB29.

Fig. S5 .
Fig. S5.Overview of custom hardware ArC TWO and experimental set-up [40].(A) Picture of fully assembled system PCBs, including base board, device-under-test interfacing daughterboard, FPGA development board and power supply board (B) Scanning electron microscope (SEM) image of stand-alone memristors.The top electrode (TE) of a device is highlighted in green and the bottom electrode (BE) in blue; the area of their intersection identifies a memristive device, with a zoomed-in view of the area shown.(C) Memristive array packaged in a PLCC68 package.(D) Experimental set-up: the arrows indicate the flow of the signal.The neural signal is generated with an arbitrary signal generator, passed to the filter and amplification stage and then directed to the memristive chip.

Fig. S6 .
Fig. S6.Biasing of a memristor device with Local Field Potential to extract auditory cue patterns.(A) the amplified Local Field Potential signal biasing the RRAM device, and (B) the resistive state of the RRAM device.The green dashed lines mark moments when auditory cues were presented to the rat.(C-H) Zoom-ins of the experiment showcasing details of the memristive encoding of LFP events.allowing for the identification of neural activity responses triggered by the auditory cues.

Fig. S7 :
Fig. S7: Receiver Operating Characteristic for "maxdrop" detection strategy.(A) Different batch sizes ranging from 70 to 490.(B) Optimization process to extract the optimum threshold value using the min distant tangent method.Here, the optimized threshold setting is 0.03.

Fig
Fig. S8.Receiver Operating Characteristic for "maxdiff" detection strategy.(A) Different batch sizes ranging from 70 to 490.(B) Optimization process to extract the optimum threshold value using the min distance secant method.Here, the optimum threshold value was identified as 0.01.

Fig
Fig. S9.Receiver Operating Characteristic for "batch" detection strategy.(A) Different batch sizes ranging from 70 to 490.(B) Optimization process to extract the optimum threshold value using the min distance secant method.Here, the optimum threshold value was identified as 0.022.

Fig. S11 .
Fig. S11.Device variability analysis example 1.(A) Channel WB29 LFP signal and (B) corresponding memristive resistance state.Notably, the selected memristor presents a higher resistance range, characterized by low resistive range of about  .This higher resistance would directly contribute to lower power consumption during memristor programming and reading phases.(C) ROC curves of the three methods: "maxdiff", "maxdrop" and "batch".(D) Performance metrics setting the threshold at  = ..Detection success is not influenced by memristor resistive range but by resistance changes, ensuring consistent performance and potential power savings irrespective of device variability.

Fig. S13 .
Fig. S13.Channel variability analysis, example 1. (A) Channel WB27 was input to a memristive device, (B) and the resistive response of the device was monitored.We can observe the signal was similar to the initial channel WB27, and the resistance successfully performs encoding of the LFP event class within the light blue windows.(C) ROC curves using "maxdiff", "maxdrop" and "batch".(D) Optimization process to select an optimum threshold, in this case equal to  = ..(E) Detection metrics for the "batch" method.

Fig. S15 .
Fig. S15.System splitting into blocks for power and energy evaluation.

Fig. S16 .
Fig. S16.Analysis of LFP Voltage Peaks and RRAM Detection Correlation.(A) Extract of LFP data highlighting instances where detections are missed, particularly during low voltage peak events.The yellow markers indicate individual detection points, while the numerical labels beneath the panel represent the maximum voltage () for each corresponding event.(B) A scatter plot demonstrating the positive correlation between the maximum voltage of LFP Events and the number of detections per batch, suggesting higher detection rates with increased voltage levels.
The clock frequency was set to 500 Hz.

Table S3 . Power and Energy-per-operation evaluation for blocks depicted in Fig. S14.
. Post-processing and thresholding present the values for 20nm ASIC implementation.